Welcome to AsicGuru.com

On Asicguru.com You will find some good material related to Asic Design and Verification. Here you will some good tutorials, examples on

1. System Verilog Tutorial - In System Verilog Section you will find tutorials on Sytem verilog constructs, Classes, OOPS, Functional Coverage, Interface, examples etc
   1. System Verilog Classes and OOPS concepts
   2. Functional Coverage
   3. Randomization
   4. Interfae
2. Open Vera - In Open Vera Secion you will find tutorial on open vera language, contstructs, arrays, classes, interfaces etc
3. Verification Methodologies
   
   1. OVM Tutorial (Open Vera Methodology)
   2. VMM Tutorial (Verification manual methodology)
4. Verilog
5. Verification Basics
6. Scripting Tutorial - Perl, Python
   1. Perl Tutorial
   2. Makefile
   3. Bash
   4. Python

This site is maintained by Puneet Aggarwal from Bangalore, India. I am working as Senior Design Engineer with AMD. I have done BTech in computer engg. from Kurukshetra University. Any comments or feeback please write to me at er.punit at gmail.com.

Click here to view my linked in profile : http://in.linkedin.com/in/puneetworld

Some sections of site are still incomplete and some of them need to be reviewed. If you can help me out with something please do drop me a mail at er.punit at gmail.com.